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White Electronic Designs
1GB - 2x64Mx64, SDRAM UNBUFFERED
FEATURES
PC100 and PC133 compatible Burst Mode Operation Auto and Self Refresh capability LVTTL compatible inputs and outputs Serial Presence Detect with EEPROM Fully synchronous: All signals are registered on the positive edge of the system clock Programmable Burst Lengths: 1, 2, 4, 8 or Full Page Available with "WP" write protect on pin 81 option * W3DG63126V-D2 3.3V 0.3V Power Supply 168 Pin DIMM JEDEC * PCB: 30.50mm (1.20in)
NOTE: Consult factory for availability of: * Lead-free products * Vendor source control option * Industrial temperature option
W3DG64126V-D2
DESCRIPTION
The W3DG64126V is a 2x64Mx64 synchronous DRAM module which consists of sixteen 64Mx8 SDRAM components in TSOP II package and one 2K EEPROM in an 8 Pin TSSOP package for Serial Presence Detect which are mounted on a 168 Pin DIMM multilayer FR4 Substrate.
* This product is subject to change without notice.
PIN CONFIGURATIONS (FRONT SIDE/BACK SIDE)
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Front VSS DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 DQ8 VSS DQ9 DQ10 DQ11 DQ12 DQ13 VCC DQ14 DQ15 *CBO *CB1 Vss NC NC VCC WE# DQM0 Pin 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 Front DQM1 CS0# DNU VSS A0 A2 A4 A6 A8 A10/AP BA1 VCC VCC CK0 VSS DNU CS2# DQM2 DQM3 DNU VCC NC NC *CB2 *CB3 VSS DQ16 DQ17 Pin 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 Front DQ18 DQ19 VCC DQ20 NC *VREF CKE1 VSS DQ21 DQ22 DQ23 VSS DQ24 DQ25 DQ26 DQ27 VCC DQ28 DQ29 DQ30 DQ31 VSS CK2 NC ***WP **SDA **SCL VCC Pin 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 Back VSS DQ32 DQ33 DQ34 DQ35 VCC DQ36 DQ37 DQ38 DQ39 DQ40 VSS DQ41 DQ42 DQ43 DQ44 DQ45 VCC DQ46 DQ47 *CB4 *CB5 VSS NC NC VCC CAS# DQM4 Pin 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 Back DQM5 CS1# RAS# VSS A1 A3 A5 A7 A9 BA0 A11 VCC CK1 A12 VSS CKE0 CS3# DQM6 DQM7 *A13 VCC NC NC *CB6 *CB7 VSS DQ48 DQ49 Pin 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 Back DQ50 DQ51 VCC DQ52 NC *VREF DNU VSS DQ53 DQ54 DQ55 VSS DQ56 DQ57 DQ58 DQ59 VCC DQ60 DQ61 DQ62 DQ63 VSS CK3 NC **SA0 **SA1 **SA2 VCC
PIN NAMES
A0 - A12 BA0-1 DQ0-63 CK0-CK3 CKE0, CKE1 CS0# - CS3# RAS# CAS# WE# DQM0-7 VCC VSS SDA SCL DNU NC WP Address input (Multiplexed) Select Bank Data Input/Output Clock input Clock Enable input Chip select Input Row Address Strobe Column Address Strobe Write Enable DQM Power Supply Ground Serial data I/O Serial clock Do not use No Connect Write Protect
* These pins are not used in this module. ** These pins should be NC in the system which does not support SPD. *** WP available on the W3DG63126V-D2 only.
White Electronic Designs Corp. reserves the right to change products or specifications without notice. January 2005 Rev. 1 1 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
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FUNCTIONAL BLOCK DIAGRAM
CS1# CS0# DQM0
W3DG64126V-D2
DQM4
DQM
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQM1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 CS3# CS2# DQM2 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
CS#
DQM
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
CS#
DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQM5
DQM
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
CS#
DQM
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
CS#
DQM
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
CS#
DQM
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
CS#
DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47
DQM
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
CS#
DQM
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
CS#
DQM6
DQM
DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQM3 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
CS#
DQM
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
CS#
DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQM7
DQM
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
CS#
DQM
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
CS#
DQM
DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
CS#
DQM
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
CS#
DQM
DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
CS#
DQM
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
CS#
A0 ~ A12, BA0 & 1 RAS# CAS# WE# CKE0
SDRAM SDRAM
SCL
VCC
SDRAM SDRAM 8SDRAM
10K
WP A0
SDA A1 A2
WP
SA0 SA1 SA2
CKE1
10 DQn
VCC One 0.1uF Capacitors per each SDRAM Vss To all SDRAMs
8SDRAM SDRAM
10 CK0/1/2/3
Every DQpin of SDRAM
SDRAM SDRAM SDRAM
1.5pF
White Electronic Designs Corp. reserves the right to change products or specifications without notice. January 2005 Rev. 1 2 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
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ABSOLUTE MAXIMUM RATINGS
Parameter Voltage on any pin relative to VSS Voltage on VCC supply relative to VSS Storage Temperature Power Dissipation Short Circuit Current Symbol VIN, VOUT VCC, VCCQ TSTG PD IOS
W3DG64126V-D2
Value -1.0 ~ 4.6 -1.0 ~ 4.6 -55 ~ +150 8 50
Units V V C W mA
Note: Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS
Voltage Referenced to: VSS = 0V, 0C TA +70C
Parameter Supply Voltage Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Input Leakage Current Symbol VCC VIH VIL VOH VOL ILI Min 3.0 2.0 -0.3 2.4 -- -10 Typ 3.3 3.0 -- -- -- -- Max 3.6 VCCQ+0.3 0.8 -- 0.4 10 Unit V V V V V A 1 2 IOH = -2mA IOL = -2mA 3 Note
Note: 1. VIH (max)= 5.6V AC. The overshoot voltage duration is 3ns. 2. VIL (min)= -2.0V AC. The undershoot voltage duration is 3ns. 3. Any input 0V VIN VCC Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
CAPACITANCE
TA = 25C, f = 1MHz, VCC = 3.3V, VREF=1.4V 200mV
Parameter Input Capacitance (A0-A12) Input Capacitance (RAS#,CAS#,WE#) Input Capacitance (CKE0-CKE1) Input Capacitance (CK0-CK3) Input Capacitance (CS0#-CS3#) Input Capacitance (DQM0-DQM7) Input Capacitance (BA0-BA1) Data input/output capacitance (DQ0-DQ63) Symbol CIN1 CIN2 CIN3 CIN4 CIN5 CIN6 CIN7 COUT Max 66 66 66 16 21 15 66 15 Unit pF pF pF pF pF pF pF pF
White Electronic Designs Corp. reserves the right to change products or specifications without notice. January 2005 Rev. 1 3 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
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IDD SPECIFICATIONS AND CONDITIONS
VCC, VCCQ = +3.3V 0.3V; SDRAM component values only MAX PARAMETER/CONDITION OPERATING CURRENT: Active Mode; Burst = 2; READ or WRITE; tRC = tRC (MIN) STANDBY CURRENT: Power-Down Mode; All device devicebanks idle; CKE = LOW STANDBY CURRENT: Active Mode; CKE = HIGH; CS# = HIGH; All device banks active after tRCD met; No accesses in progress OPERATING CURRENT: Burst Mode; Continuous burst; READ or WRITE; All device banks active AUTO REFRESH CURRENT CKE = HIGH; CS# = HIGH SELF REFRESH CURRENT: CKE < 0.2V
Notes: 1. Measured with outputs open. 2. Refresh period is 64ms.
W3DG64126V-D2
SYMBOL IDD1 IDD2 IDD3 IDD4 IDD5 IDD6 IDD7
7 1,920 56 720 2,000 3,920 96 96
7.5 1,760 56 720 1,840 3,920 96 96
10 1,760 56 720 1,840 3,920 96 96
UNITS mA mA mA mA mA mA mA
NOTES 1
1 2
tRFC = tRFC (MIN) tRFC = 7.8125s
White Electronic Designs Corp. reserves the right to change products or specifications without notice. January 2005 Rev. 1 4 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
VCC, VCCQ = +3.3V 0.3V AC CHARACTERISTICS PARAMETER Access timefrom CLK (pos.edge) CL = 3 CL = 2 Address hold time Address setup time CLK high-level width CLK low-level width Clock cycle time CL = 3 CL = 2 CKE hold time CKE setup time CS#, RAS#, CAS#, WE#, DQM hold time CS#, RAS#, CAS#, WE#, DQM setup time Data-in hold time Data-in setup time Data-out high-impedance time CL = 3 CL = 2 Data-out low-impedance time Data-out hold time (load) Data-out hold time (no load) ACTIVE to PRECHARGE command ACTIVE to ACTIVE command period ACTIVE to READ or WRITE delay Refresh period AUTOREFRESH period PRECHARGE command period ACTIVE bank a to ACTIVE bank b command Transition time WRITE recovery time SYMBOL tAC(3) tAC(2) tAH tAS tCH tCL tCK(3) tCK(2) tCKH tCKS tCMH tCMS tDH tDS tHZ(3) tHZ(2) tLZ tOH tOHN tRAS tRC tRCD tREF tRFC tRP tRRD tT tWR 1 2.7 1.8 37 60 15 64 66 15 14 0.3 1 CLK + 7ns 14 Exit SELF REFRESH to ACTIVE command tXSR 67 1.2 120,000 0.8 1.5 2.5 2.5 7 7.5 0.8 1.5 0.8 1.5 0.8 1.5 5.4 5.4 1 2.7 1.8 44 66 20 64 66 20 15 0.3 1 CLK + 7.5ns 15 75 1.2 120,000 MIN 7 MAX 5.4 5.4 0.8 1.5 2.5 2.5 7.5 10 0.8 1.5 0.8 1.5 0.8 1.5 5.4 6 1 2.7 1.8 50 66 20 64 66 20 15 0.3 MIN 7.5 MAX 5.4 6 1 2 3 3 8 10 1 2 1 2 1 2 MIN
W3DG64126V-D2
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
10 MAX 6 6 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns 6 6 ns ns ns ns ns 120,000 ns ns ns ms ns ns ns 1.2 ns 7 24 28 10 10 23 23 NOTE 27
1 CLK + 7.5ns 15 80 ns ns
25 20
White Electronic Designs Corp. reserves the right to change products or specifications without notice. January 2005 Rev. 1 5 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
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AC FUNCTIONAL CHARACTERISTICS
VCC, VCCQ = +3.3V 0.3V PARAMETER READ/WRITE command to READ/WRITE command CKE to clock disable or power-down entry mode CKE to clock enable or power-down exit setup mode DQM to input data delay DQM to data mask during WRITEs DQMto data high-impedance during READs WRITE command to input data delay Data-into ACTIVE command Data-into PRECHARGE command Last data-in to burst STOP command Last data-in to new READ/WRITE command Lastdata-into PRECHARGE command LOADMODEREGISTER command to ACTIVE or REFRESH command Data-out to high-impedance from PRECHARGE command CL = 3 CL = 2 SYMBOL tCCD tCKED tPED tDQD tDQM tDQZ tDWD tDAL tDPL tBDL tCDL tRDL tMRD tROH(3) tROH(2) 7 1 1 1 0 0 2 0 4 2 1 1 2 2 3 2 7.5 1 1 1 0 0 2 0 5 2 1 1 2 2 3 2
W3DG64126V-D2
10 1 1 1 0 0 2 0 5 2 1 1 2 2 3 2
UNITS tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK
NOTES 17 14 14 17 17 17 17 15, 21 16, 21 17 17 16, 21 26 17 17
White Electronic Designs Corp. reserves the right to change products or specifications without notice. January 2005 Rev. 1 6 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
Notes 1. All voltages referenced to VSS. 2. This parameter is sampled. VCC, VCCQ = +3.3V; TA = 25C; pin under test biased at 1.4V; f = 1 MHz. 3. IDD is dependent on output loading and cycle rates. Specified values are obtained with mini-mum cycle time and the outputs open. 4. Enables on-chip refresh and address counters. 5. The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range is ensured. 6. An initial pause of 100s is required after power-up, followed by two AUTO REFRESH commands, before proper device operation is ensured. (VCC and VCCQ must be powered up simultaneously. VSS and VSSQ must be at same potential.) The two AUTO REFRESH command wake-ups should be repeated any time the tREF refresh requirement is exceeded. 7. AC characteristics assume tT = 1ns. 8. In addition to meeting the transition rate specification, the clock and CKE must transit between VIH and VIL (or between VIL and VIH) in a mono-tonic manner. 9. Outputs measured at 1.5V with equivalent load: Q 50pF
W3DG64126V-D2
10. tHZ defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL. The last valid data element will meet tOH before going High-Z. 11. AC timing and IDD tests have VIL = 0V and VIH = 3V with timing referenced to 1.5V crossover point. If the input transition time is longer than 1ns, then the timing is referenced at VIL (MAX) and VIH (MIN) and no longer at the 1.5V crossover point. 12. Other input signals are allowed to transition no more than once every two clocks and are other-wise at valid VIH or VIL levels. 13. IDD specifications are tested after the device is properly initialized. 14. Timing actually specified by tCKS; clock(s) specified as a reference only at minimum cycle rate. 15. Timing actually specified by tWR plus tRP; clock(s) specified as a reference only at minimum cycle rate.
16. Timing actually specified by tWR. 17. Required clocks are specified by JEDEC functionality and are not dependent on any timing parameter. 18. The IDD current will increase or decrease proportionally according to the amount of frequency alteration for the test condition. 19. Address transitions average one transition every two clocks. 20. CLK must be toggled a minimum of two times during this period. 21. Based on tCK = 10ns for 10, and tCK = 7.5ns for 7 and 7.5. 22. VIH overshoot: VIH (MAX) = VCCQ + 2V for a pulse width 3ns, and the pulse width cannot be greater than one third of the cycle rate. VIL under-shoot: VIL (MIN) = -2V for a pulse width 3ns. 23. The clock frequency must remain constant (stable clock is defined as a signal cycling within timing constraints specified for the clock pin) during access or precharge states (READ, WRITE, including tWR, and PRECHARGE commands). CKE may be used to reduce the data rate. 24. Auto precharge mode only. The precharge timing budget (tRP) begins 7ns for 7; 7.5ns for 7.5 and 7.5ns for 10 after the first clock delay, after the last WRITE is executed. May not exceed limit set for precharge mode. 25. Precharge mode only. 26. JEDEC and PC133, PC100 specify three clocks. 27. tAC for 7/7.5 at CL = 3 with no load is 4.6ns and is guaranteed by design. 28. Parameter guaranteed by design.
White Electronic Designs Corp. reserves the right to change products or specifications without notice. January 2005 Rev. 1 7 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
ORDERING INFORMATION
Part Number W3DG64126V10D2 W3DG64126V7D2 W3DG64126V75D2 Speed 100MHz 133MHz 133MHz CAS Latency CL=2 CL=2 CL=3 Height* 30.48 (1.20") 30.48 (1.20") 30.48 (1.20") Part Number W3DG63126V10D2 W3DG63126V7D2 W3DG63126V75D2
W3DG64126V-D2
Speed 100MHz 133MHz 133MHz
CAS Latency CL=2 CL=2 CL=3
Height* 30.48 (1.20") 30.48 (1.20") 30.48 (1.20")
NOTE: 1 * Consult Factory for availability of lead-free products. (F = Lead-Free, G = RoHS Compliant) 2 * Product specific part numbers are available for source control if needed, please consult factory for the correct part number if a specific component vendor is preferred. 3 * Consult factory for availability for industrial temperature (-40C to 85C) options
NOTE: Available with "WP" Write Protect on pin 81.
PACKAGE DIMENSIONS
133.48 (5.255 MAX.) 3.18 (0.125) (2X) 3.99 (0.157) (2X)
3.81 (0.150) MAX.
30.48 (1.200) 17.78 MAX. (0.700)
P1
11.43 (0.450) 8.89 (0.350)
36.83 (1.450) 6.35 (0.250) 42.16 (1.660) 115.57 (4.550) 6.35 (0.250)
54.61 (2.150)
3.99 (0.157 MIN.) 1.27 0.10 (0.050 0.004)
*ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES)
White Electronic Designs Corp. reserves the right to change products or specifications without notice. January 2005 Rev. 1 8 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
Document Title
1GB - 2x64Mx64, SDRAM UNBUFFERED
W3DG64126V-D2
Revision History Rev #
Rev A Rev B Rev 0
History
Created Corrected mechanical drawing 0.1 Update CAP and IDD specs 0.2 Moved from Advanced to Preliminary
Release Date
5-3-02 5-21-02 12-04
Status
Advanced Advanced Preliminary
Rev 1
1.1 Added lead-free and RoHS notes 1.2 Added source control notes 1.3 Added industrial temperature options 1.4 Moved Preliminary to Final
1-05
Final
White Electronic Designs Corp. reserves the right to change products or specifications without notice. January 2005 Rev. 1 9 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com

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